1. Field of the Invention
The present invention relates to a method and apparatus for detecting a timeout of a reception packet in an ATM (Asynchronous Transfer Mode) communication controller for receiving a packet formed into an ATM cell in an ATM network.
2. Description of the Prior Art
ATM (Asynchronous Transfer Mode) which is a multiplex transfer scheme for digital information in B-ISDN (broadband ISDN) allows efficient processing in accordance with the amount of information to be transferred because transfer operation need not be synchronous with the bit rate of a network. ATM is therefore widely used for high-speed, broadband communication services.
FIG. 1 shows the arrangement of an ATM network, which includes an ATM communication controller for connecting a plurality of ATM terminals 21a to 21c to a plurality of ATM servers 20a and 20b through a plurality of ATM switches 22a to 22c. Note that reference numerals 23a to 23f denote packets formed into ATM cells.
On the transmission side of each ATM communication apparatus, as shown in FIG. 2, a packet is segmented into ATM cells each consisting of a 5-byte header and a 48-byte payload. These ATM cells are then transmitted through a line. Each ATM cell incorporates a number called a VPI/VCI which is used to identify a virtual connection. With this number, communication of each cell between a transmission terminal and a reception terminal is realized.
In such an ATM network, a cell of this packet in a given connection may be delayed or discarded because of some kind of abnormality in the line or apparatus. In this case, all of the ATM cells may not arrive at the reception side. For this reason, a timeout of an ATM packet must be detected to terminate the processing for this connection.
As disclosed in, for example, xe2x80x9cUsers"" Manual xcexcPD98401 Local ATM SAR Chip (NEASCOT-S10)xe2x80x9d, on the reception side of an ATM communication controller, a conventional timeout detecting section for such an ATM reception packet is used to define the time required to reassemble ATM cells into a packet, monitor in hardware whether the monitored time has exceeded the allowable time, and notify the upper layer of a timeout upon detecting it.
FIG. 3 is a block diagram showing an example of the arrangement of the ATM communication controller.
The ATM communication controller is made up of a device PHY 28 having an ATM physical layer function, an SAR (Segmentation And Reassembly) receiving section 24 for performing reception determination on the basis of the VPI/VCI value in the header of a received ATM cell, performing conversion to a VPI/VCI identification number (to be referred to as a VC hereinafter), detecting various types of errors, and reassembling ATM cells into a packet, an SAR transmitting section 25 performs ATM cell segmentation of a transmission packet and transmission cell rate control, a control memory 27 storing various pieces of information (e.g., an address for DMA and the flag of the first cell) used in the SAR receiving section 24 and the SAR transmitting section 25, and a DMA controller 26 for performing interface control with respect to a system bus 31 to which the SAR receiving section 24, the SAR transmitting section 25, a CPU 29, and system memory 30 are connected.
Upon reception of a cell, the SAR receiving section 24 checks the VPI/VCI value in the header. The payload of the reception cell for which reception is permitted is read by the DMA controller 26 and is DMA-transferred to the system memory 30 through the system bus 31.
FIG. 4 is a block diagram showing the arrangement of a conventional ATM reception packet timeout detecting apparatus.
The ATM reception packet timeout detecting apparatus is incorporated in the SAR receiving section 24. This apparatus includes a T1 register 16 in which an allowable time for a timeout is set, a TS register 17 for storing the start time of xe2x80x9cthe VC through which reception was started earliestxe2x80x9d, an adder 10 for adding the value in the T1 register 16 to the value in the TS register 17, a timer section 6 having a counter 7 that is incremented in synchronism with a system clock 19 supplied from the system bus 31 side, and a comparator 18 for comparing the output value from the adder 10 with the counter value of the timer section 6.
The control memory 27 is divided into areas in units of VCs. Each VC information is stored in a corresponding area (to be referred to as a VC table hereinafter). The parameters associated with timeout detection in each of VC tables 15a to 15c include the E bit for enabling timeout detection and linking the corresponding VC to a link list, the reception start time of a packet, i.e., the arrival time (TS) of the first cell of the packet, and forward/backward pointers (EP/BP) for forming a link list.
The SAR receiving section 24 further includes a header/payload separating section 11 for separating the header and payload of a reception cell, a VPI/VCI-VC converter 12 for converting the VPI/VCI extracted from the header of the reception cell into a corresponding VC, and a reception data FIFO 13 for storing the payload of the reception cell until execution of DMA.
The operation of the conventional timeout detecting apparatus shown in FIG. 4 will be described next.
A timeout of a reception packet is detected by a scheme of forming a link list using forward/backward pointers (FP/BP) in the corresponding VC table. In these pointers, the number of a VC through which reception was started earlier and the number of a VC through which reception was started later are respectively stored.
When a cell is received, the E bit is read out from the VC table corresponding to the reception VC. If the E bit is set and the cell is the head of a new packet, the reception VC is written in the TS area of the VC table corresponding to this VC while the counter value of the timer section 6 at this time point is regarded as the current time. If, for example, this link list has no VC, the reception VC is written in the TS register 17 at this time. After the pointers in the VC table are updated, this VC is added to the end of the link list. That is, xe2x80x9cthe VC through which reception was started earliestxe2x80x9d is always the head of a link list, whereas xe2x80x9cthe VC through which reception was started latestxe2x80x9d is linked to the end of the link list.
If the last cell of the packet arrives within the allowable time for a timeout which is set in the T1 register 16, the pointers of the corresponding VC and preceding and succeeding VCs are updated, and this VC is removed from the link list. If, for example, xe2x80x9cthe VC through which reception was started earliestxe2x80x9d is deleted from the link list, the TS register 17 is rewritten with the reception start time of the next VC to be linked.
A timeout is therefore detected first from the VC at the head of the link list, i.e., xe2x80x9cthe VC through which reception was started earliestxe2x80x9d. For this reason, the value obtained from the adder 10 by adding the reception start time of this VC, written in the TS register 17, to the allowable time for a timeout set in the T1 register 16, is input to an input terminal A of the comparator 18, while the counter value of the timer section 6 indicating the current time is input to an input terminal B of the comparator 18. A timeout can be detected by comparing the two values. If the inputs to the inputs terminals A and B of the comparator 18 are equal to each other, a timeout is detected from xe2x80x9cthe VC through which reception was started earliestxe2x80x9d.
In the conventional detecting apparatus described above, however, timeout detection cannot be performed in accordance with the cell rate or packet length in each VC. Assume that in the arrangement shown in FIG. 4, the periods of time required for reassembly after proper reception of packets through the respective VCs are respectively 2 msec for VCi; 4 msec for VCj; and 8 msec for VCk. In this case, the allowable time for a timeout must be set to 8 msec. Even if, therefore, it takes 5 msec to receive a packet through VCi, no timeout is detected. In addition, even if a cell is actually discarded from VCi, and reception is not complete, no timeout can be detected before a lapse of 8 msec. That is, accurate timeout detection cannot be performed in units of VCs.
This is because only one value can be set as a timeout allowable time for a reception packet with respect to a plurality of VCs.
The present invention has been made in consideration of the above problems in the prior art, and has as its object to provide a timeout detecting method and apparatus which can accurately perform timeout detection in units of reception VCs during the packet reassembly time, i.e., the time interval between reception of a first cell and reception of a last cell, in accordance with the cell rate of each reception VC and the packet length in an ATM communication controller.
In order to achieve the above object, according to the first basic aspect of the present invention, there is provided an ATM reception packet timeout detecting method comprising detecting a timeout of an ATM reception packet by using a CAM (Contents Addressable Memory).
In order to achieve the above object, according to the second basic aspect of the present invention, there is provided an ATM reception packet timeout detecting apparatus comprising (a) a CAM made up of a selector for switching input data in accordance with a write/search mode, a cell array in which a timeout detection time is registered, an address decoder for decoding a write/read address of contents of the cell array from a reception VC, and a priority encoder for outputting a coincidence signal and a coincidence address on the basis of outputs from the cell array, (b) a write/search mode switching section, (c) a timer section having a counter that is incremented in synchronism with a system clock supplied from a system bus side, and (d) an adder for adding the timeout allowable time for each VC to a counter value of the timer section.
According to the present invention, a bit for enabling timeout detection in each reception VC and the timeout allowable time for a reception packet can be set, in units of VCs, in each area in which corresponding VC information is stored.
As is obvious from the respective aspects, the first effect of the present invention is that timeout detection for an ATM packet can be accurately performed in units of VCs in accordance with the cell rate of each reception VC and the packet length. This is because the timeout allowable time for an ATM reception packet can be set in units of reception VCs. If, for example, the periods of time required for reassembly after proper reception of packets through the respective VCs are respectively 2 msec for VCi; 4 msec for VCj; and 8 msec for VCk, the timeout allowable times for the respective VCs can be set to 2 ms, 4 ms, and 8 ms, respectively.
The second effect of the present invention is that since the CAM is used for the timeout detecting section, the circuit size of the timeout detecting section can be made small.
The above and many other objects, features and advantages of the present invention will become manifest to those skilled in the art upon making reference to the following detailed description and accompanying drawings in which preferred embodiments incorporating the principles of the present invention are shown by way of illustrative examples.